Novel method for analysis of printed circuit imagesMANDEVILLE, J. R.IBM journal of research and development. 1985, Vol 29, Num 1, pp 73-86, issn 0018-8646Article

Integration density limitation in 3D integrated circuits due to heat dissipationGHIBAUDO, G; JAOUEN, H; KAMARINOS, G et al.Europhysics letters (Print). 1986, Vol 2, Num 3, pp 209-211, issn 0295-5075Article

Short-term forecasting in electronicsMILOJKOVIC, Jelena; LITOVSKI, Vančo.International journal of electronics. 2011, Vol 98, Num 1-3, pp 161-172, issn 0020-7217, 12 p.Article

Trends in developing electrical actuatorsGUTT, H.-J.European transactions on electrical power engineering. 1992, Vol 2, Num 2, pp 69-76, issn 0939-3072Article

Cost-density analysis of interconnectionsMESSNER, G.IEEE transactions on components, hybrids, and manufacturing technology. 1987, Vol 10, Num 2, pp 143-151, issn 0148-6411Article

Field reduction regions for compact high-voltage IC'sSUGAWARA, Y; KAMEI, T.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 8, pp 1816-1822, issn 0018-9383, 1Article

Le câblage par fil: une nouvelle piste pour les cartes à CMS = The wiring: a new track for SMC boardsMesures (1983). 1987, Vol 52, Num 12, pp 55-61, issn 0755-219X, 4 p.Article

Edge-defined self-alignment of submicrometer overlaid devicesMALHI, S. D. S; CHATTERJEE, P. K; BONIFIELD, T. D et al.IEEE electron device letters. 1984, Vol 5, Num 10, pp 428-429, issn 0741-3106Article

Analysis of the silicon technology roadmap : How far can CMOS go ? : Les défis techniques de la microélectronique = Challenges in microelectronicsSKOTNICKI, Thomas.Comptes rendus de l'Académie des sciences. Série IV, Physique, astrophysique. 2000, Vol 1, Num 7, pp 885-909, issn 1296-2147Article

Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article

LSI layout using hierarchical design with compactionABRAITIS, L; BARILA, A.Computer-aided design. 1986, Vol 18, Num 7, pp 367-370, issn 0010-4485Article

The Economic Limit to Moore's LawRUPP, Karl; SELBERHERR, Siegfried.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 1, pp 1-4, issn 0894-6507, 4 p.Article

Trockenätzen als Alternative : Strukturieren von Polyimid = Dry etching as an alternative solution : Patterning of polyimidePÖHLS, A; HELLER, G; KÄNDLER, E et al.Metalloberfläche. 1993, Vol 47, Num 2, pp 74-77, issn 0026-0797Article

Estimation of integrated squared spectral density derivativesPARK, B. U; SINSUP CHO.Statistics & probability letters. 1991, Vol 12, Num 1, pp 65-72, issn 0167-7152Article

Problems of yield gradient estimation for truncated probability density functionsSTYBLINSKI, M. A.IEEE transactions on computer-aided design of integrated circuits and systems. 1986, Vol 5, Num 1, pp 30-38, issn 0278-0070Article

Failure modes and mechanisms for VLSI ICs. A reviewFANTINI, F; MORANDI, C.IEE proceedings. Part G. Electronic circuits and systems. 1985, Vol 132, Num 3, pp 74-81, issn 0143-7089Article

Expérience en technologie à 3 microns: un procédé CMOS 10 volts à puits n = 3 μm technology experimentation: a 10 V n-well CMOS methodBEERNAERT, D.Revue des Télécommunications. 1984, Vol 58, Num 3-4, pp 398-404, issn 0373-8582Article

Failure analysis techniques for a 3D worldHENDERSON, Christopher L.Microelectronics and reliability. 2013, Vol 53, Num 9-11, pp 1171-1178, issn 0026-2714, 8 p.Conference Paper

Fifty Years of Moore's LawMACK, Chris A.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 202-207, issn 0894-6507, 6 p.Article

Future Directions for CMOS Device Technology Development from a System Application PerspectiveNINE, Tak H.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 652003.1-652003.5, issn 0277-786X, isbn 978-0-8194-6639-6Conference Paper

Trends in IC socket designLEIDY, J.Electri.onics. 1987, Vol 33, Num 9, pp 41-42, issn 0745-4309Article

Large-output-force out-of-plane MEMS actuator arrayFUKUSHIGE, T; HATA, S; SHIMOKOHBE, A et al.SPIE proceedings series. 2004, pp 240-249, isbn 0-8194-5169-X, 10 p.Conference Paper

Formal design procedures for pass transistor switching circuitsDAMU RADHAKRISHNAN; WHITAKER, S. R; MAKI, G. K et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 2, pp 531-536, issn 0018-9200Article

Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI. II: Restructurable interconnects for RVLSI and WSIMANGIR, T. E.Proceedings of the IEEE. 1984, Vol 72, Num 12, pp 1687-1694, issn 0018-9219Article

Challenges and directions for testing ICALI, Liakot; SIDEK, Roslina; ARIS, Ishak et al.Integration (Amsterdam). 2004, Vol 37, Num 1, pp 17-28, issn 0167-9260, 12 p.Article